1. Field of Invention
The present invention relates to the distribution of clock signals in circuits where the synchronization between data and clock signals cannot be guaranteed.
2. Relevant Background
In digital circuits of increasing complexity, it is a challenge to maintain synchronization between data and clock signals throughout the circuits, essentially because of increasing parasitic capacitive influences due to decreasing distances between tracks. In order to prevent data loss, clock trees need to be carefully designed in order to approach synchronization between data and clock signals in sections of a circuit. The clock signal of a “branch” assigned to a specific section of the circuit is generated from a reference clock by delay elements that are sized to match the worst-case data delay situation in that section.
FIG. 1 schematically illustrates a typical example where synchronization between a clock signal and data signals is needed. Data signals on a data bus composed of n parallel data lines S1, S2 . . . Sn arrive at the input of a latch 10. Latch 10 is clocked by a clock signal CK.
When clock CK is low, the content of latch 10 tracks the values of signals S1-Sn as they appear at the input of the latch. At the subsequent rising edge of clock CK, the data then present in the latch is held until the next falling edge of the clock.
It is essential that the data in the latch be stable when the clock's rising edge appears. If the data is not stable when the rising edge appears, the data subsequently held in the latch will take a random value. Therefore, care should be taken in the layout of the clock line so that the rising edge at the clock input of the latch always occurs between two consecutive edges at each data input of the latch.
At an origin of data signals S1–Sn and clock CK, the data is assumed to be synchronous with clock CK, i.e. the transitions of signals S1–Sn occur simultaneously with transitions of clock CK. The data lines and clock line will usually be designed to have substantially the same length, and thus have similar capacitive and delay characteristics.
However, as the number of data lines S1–Sn increases, and the distance between the data lines decreases, the influence of parasitic capacitances 12 between the lines becomes significant. The clock line will usually not run close enough to the data lines to be affected in the same manner. As a result the transitions of the data signals will inevitably be delayed with respect to the clock signal.
As shown in FIG. 2, a conventional solution to prevent data loss in latch 10 is to delay the clock signal by inserting a buffer 14 in the clock line. Buffer 14 will be sized to insert a delay corresponding to the worst-case delay in lines S1–Sn.
This solution is however very dependent on the particular layout of the various lines and the technology used, i.e. each such buffer needs to be individually sized for every section of lines between two latches and for each technology the circuit is implemented in.
FIG. 3A is a solution for delaying the clock line that is less layout and technology dependent. The clock line CK runs between two parallel lines 16 and 18 that are connected to a fixed voltage, such as ground GND. The distance between the clock line and each of the ground lines 16 and 18 is substantially equal to the distance between two data lines S1–Sn. This distance will often be the minimal distance between tracks allowed by the technology.
With this arrangement, the transitions of the clock signal CK will be delayed by the two parasitic capacitances 12′ present between the clock line and each of the ground lines, in a similar way any of the middle data signals S1–Sn will be delayed by two parasitic capacitances 12.
However, as will be explained below with reference to FIG. 3B, this solution is not fully satisfactory and will require additional elements that make it layout and technology dependent.
What is needed, therefore, is a clock delay arrangement accounting for the worst-case delay situation of the data signals, which is independent of the layout and technology.